data cacheの例文

• The PowerPC 620 data cache was optimized for technical and scientific applications.
• This eliminates most data cache cycles for reading and writing those values.
• Storing and subsequent retrievals cost additional instructions and additional data cache cycles.
• The data cache consists of eight banks separated by 32-bit boundaries.
• The Wikipedia BigTable article is silent about data caching there too.
• It is effectively a layer on the top of data caching.
• The 32 KB data cache is dual-ported through two-way interleaving.
• Each core has a 32 KB instruction cache and a 32 KB data cache.
• The PA-8500 has a 512 KB instruction cache and a 1 MB data cache.
• The data cache is protected by error correcting code ( ECC ) and parity.
• The data cache writes to the L2 cache with its own 128-bit unidirectional bus.
• Our example system, a 2.8 GHz Pentium 4, has a 16KB primary data cache.
• All models are provided with 256 KB of data cache.
• This can lead to more data cache traffic than in an advanced stack machine implementation.
• The GFS paper ( Ghemawat et al . ) says it does no data caching.
• Both CPUs contain 16 KiB of two-way set associative instruction cache and data cache respectively.
• Haswell's L1 data cache has an associativity of eight.
• The data cache is accessed with two 128-bit buses.
• The instruction cache has a 32-byte line size, whereas the data cache has 16-byte line size.
• The TurboSPARC has a 16 KB data cache.